1. Field of the Invention
The present invention relates to a semiconductor device comprising a vertical type MOSFET.
2. Description of the Related Art
In a MOSFET, the trade-off relationship is established between an ON resistance and a withstand voltage. In general, when the withstand voltage of a MOSFET is high, an ON resistance thereof becomes large. For this reason, many proposals have been conventionally made in order to improve the relationship.
Hereinafter, a description will be given of a vertical type MOSFET disclosed in unexamined Japanese Patent Publication (KOKAI) No. 9-191109 in reference to FIG. 8.
In FIG. 8, reference numeral 1 designates an N+ type silicon substrate serving as an N+ type drain region. At one of main surfaces of the silicon substrate 1 is formed an Nxe2x88x92 type high resistant drift layer 2 on a lower stage by an epitaxial growth, and further, a lower P type buried layer 3 is formed on a surface layer of the high resistant drift layer 2. On the high resistant drift layer 2 having the P type buried layer 3 formed thereon is formed an Nxe2x88x92 type high resistant drift layer 4 on a middle stage by an epitaxial growth, and further, an upper P type buried layer 5 is formed on a surface layer of the high resistant drift layer 4. On the high resistant drift layer 4 having the P type buried layer 5 formed thereon is formed an Nxe2x88x92 type high resistant drift layer 6 on an upper stage by an epitaxial growth. Thereafter, by using a well-known technique, a P type base region 7, an N+ type source region 8, a gate oxide film 9, a gate electrode 10, an interlayer insulating film 11 and a source electrode 12 are formed on the surface layer of the high resistant drift layer 6 and over the high resistant drift layer 6, and further, a drain electrode 13 is formed on the other main surface of the silicon substrate 1.
The high resistant drift layers 2, 4 and 6 are designed such that the relationships between sharing voltages V1, V2 and V3 sharing a withstand voltage VB between the source electrode 12 and the drain electrode 13 and impurity concentrations N1, N2 and N3 satisfy the following conditions:
N1 less than 1.897xc3x971018xc3x97V1xe2x88x921.35[cmxe2x88x923]xe2x80x83xe2x80x83(1) 
N2 less than 1.897xc3x971018xc3x97V1xe2x88x921.35[cmxe2x88x923]xe2x80x83xe2x80x83(2) 
N3 less than 1.897xc3x971018xc3x97V1xe2x88x921.35[cmxe2x88x923]xe2x80x83xe2x80x83(3) 
The relationships between the impurity concentrations N1, N2 and N3 and the sharing voltages V1, V2 and V3 of the high resistant drift layers 2, 4 and 6 must satisfy that the impurity concentrations N1, N2 and N3 become lower as the sharing voltages V1, V2 and V3 become higher in accordance with the above expressions (1) to (3). Furthermore, the thickness T1 of the high resistant drift layer 2 need be great in such a manner as to prevent any reach-through. However, the present inventors simulated the interrelationship among the withstand voltage and the impurity concentration, thickness and ON resistance of the high resistant drift layer, and found that optimum values of the impurity concentration and thickness of the high resistant drift layer exist, respectively, on condition that the ON resistance is minimum at a predetermined withstand voltage.
The present invention has been accomplished to utilize the feature that optimum values of the impurity concentration and thickness of a high resistance drift layer exist, respectively, on condition that an ON resistance is minimum. An object of the present invention is to provide a novel semiconductor device in which the trade-off relationship between an ON resistance and a withstand voltage can be more improved.
Technical configurations described below are basically taken according to the present invention in order to achieve the above-described object.
A first aspect of the present invention provides a semiconductor device comprising: a semiconductor substrate serving as a drain region of one conductive type; a first high resistance drift layer of one conductive type provided on a surface of the semiconductor substrate; second to (n+1)th high resistance drift layers of one conductive type provided on the first high resistance drift layer (wherein n is an integer of 1 or more); a base region of other conductive type provided on a surface layer of the (n+1)th high resistance drift layer; a source region of one conductive type provided on a surface layer of the base region; a first high resistance buried layer of other conductive type provided on a surface layer of the first high resistance drift layer and a bottom layer of the second high resistance drift layer at a position right under the base region; second to nth high resistance buried layers of other conductive type respectively provided on surface layers of the second to nth high resistance drift layers and bottom layers of the third to (n+1)th high resistance drift layers at a position right under the base region; a gate electrode provided on the base region held between the (n+1)th high resistance drift layer and the source region via a gate oxide film; a source electrode in ohmic contact with the source region over the base region and the source region; and a drain electrode provided on the other surface of the semiconductor substrate; wherein thickness of the first high resistance drift layer being established in such a manner that a depletion layer formed within the first high resistance drift layer reaches through the drain region, when a voltage lower than a sharing voltage shared by the first high resistance drift layer out of a predetermined withstand voltage between the source electrode and the drain electrode is applied to a PN junction between the first high resistance buried layer and the first high resistance drift layer.
In the second aspect of the present invention, the thickness of the first high resistance drift layer is established in such a manner that an ON resistance becomes minimum at a predetermined withstand voltage of the semiconductor device by using a graph in which variables thereof are an ON resistance, a withstand voltage and a thickness of the first high resistance drift layer of the semiconductor device.
In the third aspect of the present invention, the thickness of the first high resistance drift layer is established in such a manner that the withstand voltage of the semiconductor device becomes maximum by using a graph in which variables thereof are an ON resistance, a withstand voltage and a thickness of the first high resistance drift layer of the semiconductor device.
In the fourth aspect of the present invention, an impurity concentration of the first high resistance drift layer is an impurity concentration at a maximum withstand voltage of the semiconductor device.
In the fifth aspect of the present invention, the thickness of the first high resistance drift layer is smaller than that of each of the second to (n+1)th high resistance drift layers.
In the sixth aspect of the present invention, an impurity concentration of the first high resistance drift layer is larger than that of each of the second to (n+1)th high resistance drift layers.
In the seventh aspect of the present invention, the semiconductor device further comprising: a plurality of guard ring layers of other conductive type provided on a surface layer of the (n+1)th high resistance drift layer so as to surround the plurality of base regions; a plurality of first buried guard ring layers of other conductive type provided on the surface layer of the first high resistance drift layer and the bottom layer of the second high resistance drift layer under the guard ring layer so as to surround the first high resistance buried layer; and a plurality of second to nth buried guard ring layers of other conductive type provided on surface layers of the second to nth high resistance drift layers and bottom layers of the third to (n+1)th high resistance drift layers under the guard ring layer so as to respectively surround the second to nth high resistance buried layers.